Marking synchronization positions in an elastic store

ABSTRACT

A method and apparatus that allows egress pointer smoothing data by evaluating the average fill of an elastic store. For one embodiment of the invention, an elastic store implements a plurality of independent FIFOs, each FIFO having a write pointer and a read pointer, the write pointer including a marking pointer field and valid flag field. An incoming byte is received to a location within a traffic memory and the write pointer is used to instruct the traffic memory to indicate that the incoming bit has been received to the location. The valid flag field is set to indicate that the value at the location is currently valid.

CLAIM OF PRIORITY

This application is a non-provisional application claiming priority to provisional application Ser. No. 60/772,145, filed on Feb. 9, 2006, entitled “METHODS AND APPARATUS FOR CONDUCTING SINGLE STATE POINTER PROCESSING, RATE ADAPTATION BY DELETION OF UNUSED OVERHEAD BYTES, TECHNIQUE FOR MARKING J1/V5 POSITIONS IN AN ELASTIC STORE, EGRESS POINTER SMOOTHING, CENTRALIZED OVERHEAD AND POINTER PROCESSING,” and application Ser. No. 11/704,732, filed on Feb. 2, 2007, entitled “EGRESS POINTER SMOOTHER”, which are herein incorporated by reference in their entirety.

FIELD

Embodiments of the invention relate generally to the field of data communication and more specifically methods and apparatuses for providing efficient network data communications.

BACKGROUND

Conventional system architecture for a Sonet/SDH system has a number of disadvantages including excessive number of logic devices, redundant processing operations, and inefficient use of memory. FIG. 1 illustrates a system architecture for a Sonet/SDH system in accordance with the prior art.

Egress Pointer Movements

An inefficient aspect of the system architecture shown in FIG. 1 is the conventional egress pointer smoothing scheme employed. When performing high order pointer processing of a SDH/Sonet frame, the presence of 3 bytes of section overhead at the start of each row of 87 payload bytes, can result in uneven pointer adjustments as the phase of line and local frame change. At the output of the elastic store there is circuitry which is generating a solid SDH frame structure which is aligned to the system clock, which has spaces in it for customer data which haven't been used as yet. Every time one of those spaces comes up the elastic store reads a byte of customer data which has been written into it by the labeler and passes it on to the point of generation block and out of the system. So if everything in the network is synchronized what will happen is the labeler will be writing one byte in at the same rate the high order pointer, or the elastic store, is writing one byte out to the rest of the network. However, due to frequency differences this is not always the case. The pointer generator checks each of the FIFOs of the elastic store, in turn, to determine if that FIFO is at or near a full threshold or an empty threshold. If either condition exists, the pointer generator will perform a pointer increment or decrement, respectively, which adds a byte into the payload or deletes a byte from the payload.

The determination is made at a precise spot within the frame, however the section overhead could be rolling past this sampling point. The sampling point is a fixed position in the outgoing frame, but the incoming frame can be moving relative to that. So as the section overhead goes past nothing is written in, but data is still being read out. The elastic store appears to empty quite quickly and pointers will be written erratically (either a burst of pointers or none) during this time. This erratic behavior may appear to change the frequency at which the customer data is arriving over a very short period or may cause bit errors.

This behavior is undesirable, and various techniques have been adopted to smooth the egress pointer adjustments.

Marking Synchronization Positions in the Elastic Store

Conventional methods of signaling the position of the synchronization bytes in the elastic store either use memory inefficiently or unduly increase system complexity. A high or low order elastic store in a SDH/Sonet system requires one byte in each frame of data to be marked for synchronization purposes. Conventionally this is the J1 byte for High Order traffic, and the V5 byte for low order traffic. This is normally achieved by adding one bit to the byte in the elastic store, and setting this bit high only when the associated byte contains the appropriate byte. This increases the width of the required memory by 1 bit. Good design practice also requires that a 1 bit parity signal is calculated for each traffic byte, and passed through the system for error checking. These two requirements mean that a conventional elastic store memory would need to be 10 bits wide (8 data bits, 1 parity bit, one flag bit). Typical memories in FPGAs are 9 or 18 bits wide. Thus a 10 bit word will need an 18 bit memory, and will use twice the memory resource that would be needed if it could be implemented using a 9 bit memory.

This disadvantage has been addressed in various ways in the prior art. When implementing ASIC designs, the designer can typically generate memories of any word width, so the need for 10 bit memories is not restrictive. In FPGA designs, the designer has the option of terminating parity on the input of the Elastic Store, and regeneration in on the output. This means that parity protection is not complete within the device, which is undesirable.

Another technique known to be used is to deliberately introduce a parity error on the byte to be labeled. Since these occur on a regular basis, and circuit on the output of the elastic store can verify that these occur when expected, and reset the deliberate changes back to their true state. Implementing this function adds significant design complexity. 10 bit RAMs are inefficient in FPGA implementations. Inverting the parity bit adds significant complexity, and can result in false diagnostic error reports within the device.

Overhead and Pointer Processing

A further disadvantage of the conventional system architecture is overhead and pointer processing. The overhead and pointer processing blocks of a SDH/Sonet system are conventionally directly coupled to the traffic path. In order to achieve high traffic throughput, a typical ASIC or FPGA will implement several traffic paths (or lanes) in parallel. Each lane will carry a portion of the overall traffic. Each lane in a high bandwidth device will contain all the logic associated with processing pointers and overhead associated with that lane. This occupies a large number of gates, but is used for only a small fraction of the payload. That is, the actual gates within the design dedicated to a particular lane are only being used 3-5% of the time, and when those gates aren't being used, identical gates in other lanes are being used.

SUMMARY

An embodiment of the invention provides an apparatus including an elastic store that implements a plurality of independent FIFOs, each FIFO having a write pointer and a read pointer, the write pointer including a marking pointer field and valid flag field. An incoming byte is received to a location within a traffic memory and the write pointer is used to instruct the traffic memory to indicate that the incoming bit has been received to the location. The valid flag field is set to indicate that the value at the location is currently valid.

Other features and advantages of embodiments of the present invention will be apparent from the accompanying drawings, and from the detailed description, that follows below.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be best understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:

FIG. 1 illustrates a system architecture for a Sonet/SDH system in accordance with the prior art;

FIG. 2 illustrates a device for effecting egress pointer smoothing in accordance with one embodiment of the invention;

FIG. 3 illustrates an elastic store design in accordance with one embodiment of the invention; and

FIG. 4 illustrates centralized overhead and pointer processing using a shared central processor in accordance with one embodiment of the invention.

DETAILED DESCRIPTION

A method and apparatus that allows egress pointer smoothing data by evaluating the average fill of an elastic store. For one embodiment of the invention, by measuring the average fill, the 3 bytes of SOH and 87 bytes of data are taken together in each sample, and the relative phase of ingress and egress frames does not impact the fill depth calculation. For one such embodiment, the calculation is performed by summing the elastic store fill over a full row. The result is 87 times the average fill level. The average can be calculated by dividing the result by 87. In an alternative embodiment, the thresholds (which are constant) are multiplied by 87. This multiplication is performed during synthesis. This allows non-integer thresholds to be used, so for example the lower threshold may be set at 3.3 rather than just 3 or 4, as in prior art schemes. For one embodiment of the invention, the size of the comparator logic is reduced by selecting thresholds that have a number of the least significant bits set to ‘0’ (binary), so that they may be ignored in the comparison.

In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Moreover, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.

Embodiments of the invention are applicable to wide range of systems in which data is communicated.

Egress Pointer Smoothing

For one embodiment of the invention, egress pointer smoothing by evaluating the average fill of an elastic store over a full payload row. For alternative embodiments the evaluation could be performed over several rows or a full frame with added logic complexity.

For one embodiment of the invention, the information related to the amount of fill in the elastic store is averaged across the length of the complete row. Therefore, as the section overhead from an incoming channel moves through the outgoing section, the average fill of the elastic store is being measured including the information of where the section overhead sits within the row. Increment/decrement decisions based on that average figure provide a smooth rate of pointers coming out even as a section overhead moves through the frame.

For one embodiment of the invention, the average value is compared to a fixed upper and lower bound and if the average exceeds an upper bound this results in an increment decision, and if the average value is less than a lower bound this results in a decrement decision.

For one embodiment, to avoid the complexity of division to obtain an average value, the upper and lower bounds, which are themselves constants, are multiplied by the number of samples the sum is compared. The number of samples depends on the type of data traffic and may be, for example, 87 for an STS-1 or 3 for a VT1.5.

FIG. 2 illustrates a device for effecting egress pointer smoothing in accordance with one embodiment of the invention. As shown in FIG. 2, the read pointer 205 and write pointer 206 are accumulating the fill level of the elastic store. An integrator 210 is included which will be used to store the elastic store depth values. At the beginning of each one of specified periods of time, which for one embodiment could be the beginning of each row, the counter is reset to zero. Then for each successive byte across the row the instantaneous value of the elastic store depth is determined and added to the integrator 210.

At a specified point, the elastic store depth is sampled by sampler 215 and the elastic store depth value is forwarded to pointer decision logic 220. Pointer decision logic 220 compares the value to a defined threshold and makes a decrement/increment decision based on that comparison. If the sum of the information in the integrator is either greater than the upper bound, an increment is performed, if the sum is between the upper bound and the lower bound, no action is taken, and if the sum is less than the lower bound a decrement is performed.

The smoothness obtained depends on the number of bytes accumulated and presents a tradeoff between smoothness and the logic required to effect it.

Marking Synchronization Positions in the Elastic Store

Embodiments of the invention, provide a signaling mechanism for marking particular bytes in the payload stream (e.g., elastic store synchronization bytes) by using a write pointer function as opposed to prior art schemes that require a flag bit in the elastic store. Embodiments of the invention allow for an elastic store that need only be 9 bits wide. The number of bits in the write pointer register or memory is doubled, plus an extra flag bit, but since this memory is typically 16 or 32 times smaller than the elastic store, the overall memory utilization is less. The extra bit indicates if a flagged byte has been written to the elastic store recently, in which case, the additional bits are used to pass the write pointer value at which the flagged byte was written, from the write to the read controller of the elastic store.

A further advantage is that the signaling mechanism can be used to signal other conditions and pass fault indication flags from the ingress port to the egress port of the elastic store.

FIG. 3 illustrates an elastic store design in accordance with one embodiment of the invention. As shown in FIG. 3, an embodiment of the invention provides an alternative method of signaling the position of the J1 through the elastic store.

The traffic memory 305 is made up of lots of separate FIFOs, with each independent FIFO having its own write pointer and read pointer. The write pointer memory in the prior art consists of one pointer (a write pointer field) which goes from, for example, zero up to 15 back to zero and keeps on repeating that. An embodiment of the invention implements a second field (a marking pointer field) in the write pointer memory 310, which, for one embodiment, is the same width as that original counter space (e.g., four bits wide), and a third field (an additional bit) for a valid flag. When an in-coming bit (e.g., a J1 bit) is to written to a particular location inside the traffic memory 305, one of these values from zero to 15, the write pointer 311 instructs the traffic memory 305 to write that information into the particular location for that channel. The information is copied into the additional field and that indicates, for example, that there is now a J1 byte at that position in the traffic memory. The valid flag bit is set to indicate that the value at the location is currently valid. This signaling method requires that only nine bits of data be put into the traffic memory 305. The read pointer memory 320 functions as in the prior art scheme. The fill comparator 330 not only compares the read pointer and the write pointer to calculate the FIFO depth, as in the prior art scheme, but also compares the read pointer to the marking pointer 312. When the fill comparator 330 detects that the read pointer has reached the particular location and that the valid flag 313 is true, this indicates that what is being read out of the traffic memory 305 is the in-coming byte that is to be marked.

Therefore, the marker bit was not placed in traffic memory 305, but is stored in the write pointer memory 310 at a location that is made visible to the fill comparator 330, which can now assert a signal indicating that the byte which has just been read by the read pointer memory 320 from the traffic memory 305 is the marked byte.

Typically, a marking event occurs approximately every 760 bytes. So since the actual traffic memory for every channel has only 16 bytes, the write pointer clears the valid flag the next time it comes around to the particular location, because it is about to overwrite the location that the marked byte had been in the last time. The read pointer then clears the valid flag. It doesn't actually have to do anything with the marking pointer as the value at that location will be changed to some new value and the valid flag will be reset.

Although the example discussed above was in reference to a single channel and particular byte of that channel, in a typical system there are hundreds of channels going on at the same time. The write pointer memory, therefore could have hundreds of marking pointers stored for individual channels. There is only one write pointer and marking pointer for each channel but there could be hundreds of them stored in the write pointer memory. The correct one, represented by the double arrow of FIG. 3 from the write pointer memory 310 to the fill comparator 330, represents the piece of information related to the channel that the read logic is currently processing.

As noted above, embodiments of the invention allow signaling additional information from the input to the output of the elastic store by using the marking pointer bytes. For example, if the valid flag 313 is zero then the timing detector block 331 ignores the marking pointer value and the read pointer does not perform a comparison. That is, there is no interpretation given to the marking pointer value. Therefore, interpretations can be assigned to its value to signal additional information. So, for example, with the valid flag of zero and with no J1 bytes in the elastic store at the minute, a marking pointer value of zero could be used to indicate normal operation and values other than zero can indicate particular fault conditions on the input of the elastic store.

Centralized Overhead and Pointer Processing

Embodiments of the invention implement a centralized processing block that processes pointers and overhead from a number of lanes. This significantly reduces the number of gates required to implement this processing in an ASIC or FPGA. An embodiment of the invention implements an off-line engine that is dedicated to processing the overhead bytes extracted from the data path.

For one embodiment of the invention, a minimal block of logic, associated with each lane, performs only those operations which must be performed on every byte (such as BIP calculation), or must be performed quickly (such as processing a pointer NDF). The vast majority of bytes do not need this speed of response and can be processed in the shared block.

For one embodiment, all other pointer and overhead bytes are tagged with an identifier, and sent to a centralized processing block. The data is sent through a FIFO, so that if bytes arrive simultaneously from several lanes, the central block can process them on a fair basis, without loosing any.

For one embodiment of the invention the centralized processing block operates on a different (e.g., slower) clock domain than the traffic processing of the lane. This allows more complex logic to complete in a single clock cycle, without the need to utilize pipelining.

For one embodiment of the invention, all pointer and overhead processing can be performed sequentially, allowing the centralized processing block to hold state information in an external or large internal memory. Using external memory for all overhead state information greatly reduces the memory requirement within the device, and allows memory intensive functions such as LO J2 path trace and TCM to be implemented without greatly increasing the size or cost of the ASIC or FPGA.

An advantage of one embodiment of the invention is that pointer and overhead processing operations do not need to be completed in 1 clock cycle, as in prior art schemes in which pointer and overhead processing operations are tightly coupled to the traffic path. A further advantage of one embodiment of the invention is that sequential processing of the pointer and overhead events facilitates event filtering by hardware, before it is reported to software, and a consistent reporting mechanism for events when they occur.

FIG. 4 illustrates centralized overhead and pointer processing using a shared central processor in accordance with one embodiment of the invention. In the processing scheme shown in FIG. 4, various processing 410 occurs within each of the data lanes 420. Because the pointer bytes and overhead bytes represent a small portion of the actual content of a frame of data coming in, the overhead processing 430 and the pointer processing 440 are directed through FIFOs 450 to a shared offline processing engine 460. For one embodiment, the overhead processing 430 and the pointer processing 440 is combined and passed down through a FIFO to the offline engine.

Each data lane may have various processing blocks that direct processing to the offline engine. So as a result, a lot of information will be flowing towards it. It'll be coming through quite often in bursts followed by a gap of time when it can process. The FIFO elements, which offer up the data arriving at the offline engine allow it to process each of the different data lanes within the design in turn.

General Matters

For one embodiment of the invention, egress pointer smoothing by evaluating the average fill of an elastic store over a full payload row. For one embodiment of the invention, the information related to the amount of fill in the elastic store is averaged across the length of the complete row and increment/decrement decisions based on that average figure provide smooth rate of pointers coming out even as a section overhead moves through the frame.

Embodiments of the invention, provide a signaling mechanism for marking particular bytes in the payload stream by using a write pointer function. For one such embodiment the elastic store need only be 9 bits wide.

Embodiments of the invention implement a centralized processing block that processes pointers and overhead from a number of lanes. One embodiment of the invention implements an off-line engine that is dedicated to processing the overhead bytes extracted from the data path.

Embodiments of the invention have been described above with various specific details. It will be appreciated that such details are examples and may be modified.

Embodiments of the invention have been described as including various operations. Many of the processes are described in their most basic form, but operations can be added to or deleted from any of the processes without departing from the scope of the invention.

The operations of the invention may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor or logic circuits programmed with the instructions to perform the operations. Alternatively, the steps may be performed by a combination of hardware and software. The invention may be provided as a computer program product that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer (or other electronic devices) to perform a process according to the invention. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnet or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing electronic instructions. Moreover, the invention may also be downloaded as a computer program product, wherein the program may be transferred from a remote computer to a requesting computer by way of data signals embodied in a carrier wave or other propagation medium via a communication cell (e.g., a modem or network connection).

While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting. 

1. A method comprising: by an elastic store having a fill comparator, a traffic memory, a write pointer memory, and a read pointer memory, implementing a plurality of independent FIFOs, each FIFO having a write pointer stored in the write pointer memory and a read pointer stored in the read pointer memory, the write pointer including a marking pointer field and valid flag field stored in write pointer memory at a location that is visible to the fill comparator; receiving an incoming byte to a location within the traffic memory; using the write pointer to instruct the traffic memory to indicate that the incoming bit has been received to the location; setting the valid flag field to indicate that the value at the location is currently valid: and marking the incoming byte upon detecting that the read pointer has reached the location and that the valid flag field is set.
 2. The method of claim 1 wherein the write pointer memory is four bits wide and the valid flag field is one bit wide.
 3. The method of claim 1 wherein the incoming bit is a J1 bit.
 4. The method of claim 1 wherein marking occurs approximately every 760 bytes.
 5. The method of claim 1 wherein a marking pointer value of zero indicates a normal operation and marking pointer values indicate corresponding fault conditions.
 6. A nontransitory machine-readable medium that provides executable instructions, which when executed by a processor, cause the processor to perform a method, the method comprising: by an elastic store having a fill comparator, a traffic memory, a write pointer memory, and a read pointer memory, implementing a plurality of independent FIFOs, each FIFO having a write pointer stored in the write pointer memory and a read pointer stored in the read pointer memory, the write pointer including a marking pointer field and valid flag field stored in write pointer memory at a location that is visible to the fill comparator; receiving an incoming byte to a location within the traffic memory; using the write pointer to instruct the traffic memory to indicate that the incoming bit has been received to the location; setting the valid flag field to indicate that the value at the location is currently valid: and marking the incoming byte upon detecting that the read pointer has reached the location and that the valid flag field is set.
 7. The nontransitory machine-readable medium of claim 6 wherein the write pointer memory is four bits wide and the valid flag field is one bit wide.
 8. The nontransitory machine-readable medium of claim 6 wherein the incoming bit is a J1 bit.
 9. The non-transitory machine-readable medium of claim 6 wherein marking occurs approximately every 760 bytes.
 10. The non-transitory machine-readable medium of claim 6 wherein a marking pointer value of zero is indicates a normal operation and marking pointer values indicate corresponding fault conditions.
 11. An apparatus comprising: an elastic store having a fill comparator, a traffic memory, a write pointer memory, and a read pointer memory and configured to implement a plurality of independent FIFOs, each FIFO having a write pointer stored in the write pointer memory and a read pointer stored in the read pointer memory, the write pointer including a marking pointer field and valid flag field stored in write pointer memory at a location that is visible to the fill comparator, the traffic memory for receiving an incoming byte to a location, wherein the write pointer instructs the traffic memory to indicate that the incoming bit has been received to the location and the valid flag field is set to indicate that the value at the location is currently valid, the apparatus further configured to mark the incoming byte upon determining that the read pointer has reached the location and that the valid flag is set.
 12. The apparatus of claim 11 wherein the write pointer memory is four bits wide and the valid flag field is one bit wide.
 13. The apparatus of claim 11 wherein the incoming bit is a J1 bit.
 14. The apparatus of claim 11 wherein marking occurs approximately every 760 bytes.
 15. The apparatus of claim 11 wherein a marking pointer value of zero is indicates a normal operation and marking pointer values indicate corresponding fault conditions; an integrator to determining an average fill value of the elastic store; and a pointer generator to perform a pointer increment operation if the average fill value is above an upper threshold, and to perform a pointer decrement operation if the average fill value is below a lower threshold. 